1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, it relates to a semiconductor memory device comprising nonvolatile semiconductor memory cells.
2. Description of the Prior Art
Specifications required to semiconductor memories are now in the process of changing following popularization of information apparatuses. In particular, a semiconductor memory mounted on a portable apparatus requires low power consumption.
A dynamic random access memory (hereinafter referred to as a DRAM) is preferably employed in consideration of its memory capacity and the cost therefore, the DRAM cannot hold data if the power is turned off, due to its characteristics.
Therefore, the DRAM must be so periodically refreshed that the same slightly consumes power even in an unused state (standby state).
On the other hand, a nonvolatile memory, which can hold data also in a power-off state, is excellent in a point that the same requires no complicated operation such as a refresh operation for holding the data.
A flash memory or a ferroelectric memory (FRAM) is regarded as a candidate for such a nonvolatile memory. Particularly the ferroelectric memory, which has some advantages in write operating speed and rewrite count compared to the flash memory, is expected as the representative for future nonvolatile memories.
FIG. 35 is a circuit diagram for illustrating a first exemplary cell structure of a conventional ferroelectric memory.
Referring to FIG. 35, a memory cell 552 includes two access transistors 568 and 570 and ferroelectric capacitors 572 and 572 provided in correspondence to the access transistors 568 and 570 respectively.
This structure is the so-called 2Tr-2C structure, and the gates of the two access transistors 568 and 570 are connected with the same word line WL. A first electrode of the ferroelectric capacitor 572 is connected to a bit line BL through the access transistor 568. A first electrode of the ferroelectric capacitor 574 is connected to a bit line /BL through the access transistor 570. Second electrodes of the ferroelectric capacitors 572 and 574 are connected to a cell plate CP.
In this structure, the two ferroelectric capacitors 572 and 574 store 1-bit data as complementary data.
FIG. 36 shows an operating waveform diagram showing an exemplary read operation of the ferroelectric memory cell 552 appearing in FIG. 35 and illustrates polarization curves of the capacitors 572 and 574.
Referring to FIGS. 35 and 36, an equalize signal BLEQ goes high between times t1 and t2, for precharging the pair of bit lines BL and /BL at low levels. At this time, the potential of the cell plate CP is at a low level.
Between times t2 and t3, the equalize signal BLEQ first goes low, and then the potential of the word line WL rises while the potential of the cell plate CP goes high. Consequently, a small potential difference takes place between the pair of bit lines BL and /BL. Between times t3 and t4, a sense amplifier activation signal SAE goes high to activate the sense amplifier 556, which in turn amplifies the small potential difference between the pair of bit lines BL and /BL for reading data to the exterior.
L data is rewritten in either one of the ferroelectric capacitors 572 and 574 for holding the L data.
Between times t4 and t5, the potential of the cell plate CP goes low for causing a sufficient potential difference between the electrodes of the capacitor 572 or 574 connected with the bit line BL or /BL carrying H data, thereby rewriting the H data.
Between times t5 and t6, the sense amplifier activation signal SAE goes low to inactivate the sense amplifier 556 and the equalize signal BLEQ goes high while the pair of bit lines BL and /BL go low together, whereby the electrodes (storage nodes) of the ferroelectric capacitors 572 and 574 opposite to the cell plate CP go low.
Namely, the potential difference between the electrodes of the ferroelectric capacitors 572 and 574 becomes zero, so that the H and L data are stored as the values of the remanent polarization of the ferroelectric capacitors 572 and 574 as shown in the polarization curves.
The memory cell 552 holds these remanent polarization values, which are nonvolatile, until the next write operation is performed, and requires no refresh operation dissimilarly to the DRAM.
Between times t6 and t7, the potential of the word line WL falls to complete the series of read operations. Even if the word line WL is not closed before the sense amplifier activation signal SAE and the equalize signal BLEQ go low and high respectively, no problem arises dissimilarly to the conventional DRAM.
The conventional ferroelectric memory can read data in the aforementioned operation, and is capable of implementing an access time of about 200 ns, although the same is slightly disadvantageous in access due to the driving of the cell plate potential CP.
Under the present circumstances, however, the conventional ferroelectric memory has some significant problems to be solved.
For example, the polarized state of the ferroelectric capacitor 572 or 574 storing the H data goes round the polarization curve and requires an operation of remarkably inverting the polarized state as shown in FIG. 36, leading to fatigue of the ferroelectric film quality.
If the operating time is lengthened, therefore, the remanent polarization value or the like on the polarization curve so remarkably changes that the memory cannot be used as a nonvolatile memory.
Thus, the read/write count is limited.
In relation to this, the ferroelectric memory is generally not in the so-called simple 1Tr-1C structure but in the cell structure for storing 1-bit data in the 2Tr-2C structure shown in FIG. 35, dissimilarly to the DRAM.
While a memory of the 1Tr-1C structure employs a reference cell which is identical in structure to memory cells for generating a reference potential, this cell is remarkably frequently accessed as compared with the remaining memory cells, and hence the characteristics of the ferroelectric film are so quickly deteriorated following fatigue that the reference cell cannot generate the normal reference potential.
In general, therefore, the ferroelectric memory has a larger chip area than a DRAM of the same capacity.
The aforementioned problem is caused since the ferroelectric memory is regularly used in a nonvolatile mode. To this end, there have been proposed some systems of making the ferroelectric memory, which has a sufficiently larger dielectric constant than capacitors employed in the general DRAM, operate similarly to the DRAM thereby preventing the ferroelectric capacitors from characteristic deterioration resulting from inversion of polarization.
In a system proposed by K. Takeuchi et al. in "Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors", IEICE Trans. Electron., Vol. E79-C, pp. 234-242 (1996), for example, a ferroelectric memory performs a read or write operation absolutely similarly to the DRAM, in a general state other than a power on/off state.
In this system, no cell plate potential may be driven but a pair of bit lines are precharged at Vcc/2 in a standby state. Such a mode of using a nonvolatile memory in an operation similar to that of the DRAM is referred to as a DRAM mode.
The most serious drawback of the DRAM mode for preventing deterioration of ferroelectric film characteristics resides in that a refresh operation is required similarly to the DRAM. If the memory is integrated into a system, a complicated operation is required for issuing an instruction or timing for the refresh operation, and the refresh operation regularly consumes power.
Japanese Patent Laying-Open No. 7-244988 (1995) discloses a system of driving only a frequently accessed area into the DRAM mode while bringing areas not accessed in excess of a constant time into the nonvolatile mode thereby suppressing power consumption following the refresh operation.
FIG. 37 is a block diagram showing the structure of the semiconductor memory device disclosed in Japanese Patent Laying-Open No. 7-244988.
The semiconductor memory device shown in FIG. 37 employs ferroelectric capacitors as information storage capacitors of memory cells and comprises a continuous refresh count control circuit 614, a mode conversion circuit 612, a mode storage memory 618 and a mode determination circuit 616, in addition to a conventional DRAM comprising a memory mat 608, an X decoder 610, a Y decoder 604, a Y switch 606, a refresh activation circuit 624, an X address selector circuit 622, a Y address selector circuit 620, a timing control circuit 626 and an input/output buffer 602.
The X address selector circuit 622 fetches and holds an address signal inputted in synchronization with a row address strobe signal.
The Y address selector circuit 620 fetches and holds an address signal inputted in synchronization with a column address strobe signal.
The X decoder 610 decodes the X address signal and selects a word line of the memory mat 608. The Y decoder 604 decodes the Y address signal, forms a column selector signal for a complementary data line of the memory mat 608, and controls the Y switch 606. The Y switch 606 connects the complementary data line selected by the column selector signal to the input/output buffer 602.
The timing control circuit 626 receives the row address strobe signal, the column address strobe signal and a write enable signal, identifies a read/write or refresh operation mode, and forms an internal timing signal corresponding thereto.
The refresh activation circuit 624 outputs a refresh address to the X decoder 610 when in the refresh mode.
The memory mat 608 is split into a plurality of memory blocks, and the mode storage memory 618 stores whether the operation mode of each memory block is the DRAM or nonvolatile mode. The continuous refresh count control circuit 614 counts the refresh operation for each memory block, and resets the count value when a read or write operation is performed for any memory cell included in each memory block.
When the refresh activation circuit 624 makes a refresh operation, the mode determination circuit 616 reads mode information of a memory block stored in the mode storage memory 618 by a refresh address signal therefore and determines whether the memory block is in the DRAM mode or the nonvolatile mode.
If the memory block is in the DRAM mode, the mode determination circuit 616 performs the refresh operation as such and makes the continuous refresh count control circuit 614 count +1.
If the memory block is in the nonvolatile mode, on the other hand, the mode determination circuit 616 omits the refresh operation. Namely, the mode determination circuit 616 omits an operation of selecting any word line or activating a sense amplifier by the X decoder 610.
When the X address selector circuit 622 accesses any memory cell for writing or reading data, the mode determination circuit 616 makes the continuous refresh count control circuit 614 reset the refresh count of the corresponding memory block to zero, and brings the mode storage memory 618 into the DRAM mode through the mode conversion circuit 612. This mode conversion can be omitted if the mode storage memory 618 is already in the DRAM mode.
When the refresh operation is performed by a predetermined count, the continuous refresh count control circuit 614 instructs the mode conversion circuit 612 to convert the mode of the memory block. In the refresh operation, the mode conversion circuit 612 temporarily raises the plate voltage of the memory block from a ground potential to a power supply potential Vcc, for example, for performing writing accompanied by inversion of the polarization of the ferroelectric capacitors in rewriting by the refresh operation.
The mode conversion circuit 612 makes the mode storage memory 618 store the nonvolatile mode.
FIG. 38 is a schematic block diagram for illustrating examples of the memory mat 608 and the continuous refresh count control circuit 614 in the conventional semiconductor memory device.
FIG. 38 illustratively shows a circuit which is applied to the memory mat 608 split in units of word lines and corresponding to an i-th word line WLi as a representative.
Referring to FIGS. 37 and 38, the continuous refresh count control circuit shown in this example is provided with a plurality of dynamic memory cells on the word line WLi identical to that for the memory mat 608, to be employed as a continuous refresh count storage circuit.
Assuming that the continuous refresh count is three, for example, two memory cells M1i and M2i are provided in a continuous refresh count FT(i) storage memory.
An FTRW circuit 634 reads counts stored in the memory cells M1i and M2i, adds +1 thereto and rewrites the results in the memory cells M1i and M2i.
In a third refresh operation when the storage information of both memory cells M1i and M2i becomes 1, a timing pulse .phi. VPL is generated for temporarily converting a plate potential VPLi of a ferroelectric capacitor CMi corresponding to the word line WLi performing refreshment to a high level in correspondence to the timing pulse .phi. VPLi through a gate circuit G supplied with a selector signal for the word line WLi in its one input.
Thus, the direction of polarization of the memory cell coupled to the word line WLi in the continuous third refresh operation is decided in correspondence to the storage information in rewriting. The refresh operation is thereafter not necessary because of non-volatization, the refresh operation is omitted.
An operation of switching the conventional semiconductor memory device from the DRAM mode to the nonvolatile mode is now described.
FIG. 39 is an operating waveform diagram showing an operation of non-volatilizing the semiconductor memory device storing H data.
FIGS. 41A and 41B illustrate polarized states of a ferroelectric film on hysteresis characteristics.
Referring to FIGS. 38, 39, 41A and 41B, the potential of the word line WLi rises from 0 V to 5 V to be selected in a state 1, whereby the potential of a bit line BLi connected with the memory cell storing the H data slightly rises and is converted to 5 V by a sense amplifier. At this time, the plate potential VPLi is 0 V. The ferroelectric capacitor Cmi enters the polarized state 1 shown in FIG. 41A.
In a state 2, the plate potential VPLi rises from 0 V to 5 V. Both electrodes of the ferroelectric capacitor Cmi are supplied with the same potential in this state 2, whereby the ferroelectric capacitor Cmi enters the polarized state 2 shown in FIG. 41B in correspondence to the voltage of 0 V.
In a state 3, the plate potential VPLi changes from 5 V to 0 V and the voltage of 5 V is applied to the electrodes of the ferroelectric capacitor Cmi again, whereby the ferroelectric capacitor Cmi enters the polarized state 3 shown in FIG. 41A.
Thus, the semiconductor memory device enters the nonvolatile mode.
The semiconductor memory device thereafter performs no refresh operation in this nonvolatile mode, whereby the potential of a storage node reduces to a low level by a leakage current in a state 4 and no voltage is applied between the electrodes of the ferroelectric capacitor Cmi, for holding information by remanent polarization as shown in the state 4 in FIG. 41B.
FIG. 40 is an operating waveform diagram of an operation for bringing the semiconductor memory device storing L data into the nonvolatile mode.
FIGS. 42A and 42B illustrate polarization of the ferroelectric film on the hysteresis characteristics.
Referring to FIGS. 40, 42A and 42B, the word line WLi is selected and its potential rises from 0 V to 5 V in a state 1. Slight change appears on the bit line BLi on the basis of the stored L data, and the sense amplifier amplifies this change to reduce the potential of the bit line BLi to 0 V. In this state, a voltage of 0 V is applied between the electrodes of the ferroelectric capacitor Cmi, which in turn enters the polarized state 1 shown in FIG. 42A.
In a state 2, the plate potential VPLi changes from 0 V to 5 V and a voltage of -5 V is applied between the electrodes of the ferroelectric capacitor Cmi, which in turn enters the polarized state 2 shown in FIG. 42B.
In a state 3, the plate potential VPLi is converted from 5 V to 0 V, whereby the potential difference between the electrodes of the ferroelectric capacitor Cmi becomes 0 V and the ferroelectric film is polarized as shown in the state 3 in FIG. 42b.
Thus, the semiconductor memory device enters the nonvolatile mode. The semiconductor memory thereafter performs no refresh operation in such a nonvolatile mode, thereby holding negative remanent polarization as storage data, as shown in the state 4 in FIG. 42B.
When the word line WLi is selected by a read operation, a slight high level is outputted to the bit line BLi with respect to a half precharge voltage of 2.5 V serving as a reference voltage in correspondence to the remanent polarization in the state 4 shown in FIG. 39 or a slight low level is outputted in the state 4 in FIG. 40 so that the sense amplifier amplifies this output for rewriting the high or low level in the ferroelectric capacitor, whereby a read signal corresponding to the direction of polarization can be obtained as shown in the state 1 in FIG. 41A or in the state 2 shown in FIG. 42B, and the semiconductor memory device thereafter operates in the DRAM mode.
In the DRAM mode, the plate potential VPLi is fixed to the ground potential of the circuit, whereby the polarization of the ferroelectric capacitor Cmi remains unchanged for storing high or low level information as a simple capacitor.
The method shown in Japanese Patent Laying-Open No. 7-244988 is adapted to equivalently recognize the time when a certain area is not accessed by counting the refresh count. However, the refresh count is decided by the external specification (user state), and hence the time for switching the DRAM mode to the nonvolatile mode depends on the external specification (user state).
Namely, the time operating in the DRAM mode fluctuates to change the power consumption.
In case of adjusting the time for switching the DRAM mode to the nonvolatile mode in response to requirement for power consumption responsive to the employment, it is difficult to remarkably change the switching time in the method described in Japanese Patent Laying-Open No. 7-244988, due to the employment of the memory cell dedicated to mode storage.
In case of a DRAM, a bit line precharge potential and a cell plate potential are generally Vcc/2. When a ferroelectric memory is used in the nonvolatile mode, on the other hand, the bit line precharge potential and the cell plate potential are generally Vcc or the ground potential.
In case of switching the mode following such conventional use of the DRAM or the ferroelectric memory, the levels of the bit line precharge potential and the cell plate potential must also be switched at the same time.